library ieee;
use ieee.std_logic_1164.all;

library lib_ExpoRNS;

entity k_bench is  
end k_bench;

architecture k_bench1 of k_bench is
  component  k_Unit is
    
    generic (
      Z : positive := 10);

    port (
      n : in std_logic_vector(Z-1 downto 0);
      S : out std_logic_vector(8 downto 0));

  end component;



  signal n_in : std_logic_vector(9 downto 0);
  signal s_out : std_logic_vector(8 downto 0);

begin  -- k_bench
  mapk: k_Unit port map (n_in,s_out);
  process
    constant delay: time :=10 ns;    
  begin
    n_in <= "0000000001";
    wait for delay;
    n_in <= "0000000011";
    wait for delay;
    n_in <= "0000100001";
    wait for delay;
  end process;    
  

end k_bench1;
